View LH540203D20_3150001.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

lh540203 cmos 2048 9 asynchronous fifo features fast access times: 15/20/25/35/50 ns fast- fall-thr ough time architecture based on cmos dual-port sram technology input port and output port have entirely independent t iming expandable in width and depth full, half-full, and empty status flags data retransmission capability ttl-compatible i/o pin and funct ionally compatible with sharp lh5498 and with am/idt/m s7203 control signals assertive-low for noise immunity packages: 28-pin, 300-mil pdip 28-pin, 300-mil soj * 32-pin plcc pin connections functional description the lh540203 is a fifo (first-in, first-out) memory device, based on fully-static cmos dual-port sram tech- nology, capable of storing up to 2048 nine-bit words. it follows the industry-standard architecture and package pinouts for nine -bit asynchronous fifos. each nine-bit lh540203 word may consist of a standard eight-bit byte, together with a parity bit or a block-marking/framing bit. the input and output ports operate entirely inde- pendently of each other, unless the lh540203 b ecomes either totally full or else totally empty. data flow at a port is initiated by asserting either of two asynchronous, as- sertive-low control inputs: write ( w) for data entry at the input port, or read ( r) for data retrieval at the output port. full, half-full, and empty status flags monitor the extent to which the internal memory has been filled. the system may make use of these status outputs to avoid the risk of data loss, which otherwise might occur either by attempting to write additional words into an already-full lh540203, or by attempting to r ead additional words from an already-empty lh540203. when an lh540203 is operating in a depth-cascaded configuration, the half-full flag is not available. 540203-2d 1 2 3 4 5 6 7 8 9 10 11 12 13 14 w d 8 d 3 d 2 d 1 d 0 xi ff q 0 q 1 q 2 q 3 q 8 v ss 28 27 26 25 24 23 22 21 20 19 18 17 16 15 d 7 fl/rt rs ef xo/hf q 5 q 4 r q 6 q 7 d 6 d 5 d 4 v cc 28-pin pdip 28-pin soj * top view figure 1. pin connections for pdip and soj * packages 5 6 7 8 9 10 d 2 xi ff 11 2 3 4 32 31 30 29 28 27 26 25 24 nc ef d 3 d 8 w nc * v cc d 4 d 5 14 15 16 20 19 18 17 fl/rt rs 23 xo/hf 22 21 12 nc 13 1 q 3 q 8 v ss nc * r q 4 q 5 540203-3d d 1 d 0 q 0 q 1 q 2 d 6 d 7 q 7 q 6 32-pin plcc top view note: * = no external electrical connections are allowed. figure 2. pin connections for plcc package * this is a final data sheet; except that all references to the soj pa ckage have advance info rmation status. 1
data words are read out from the lh540203s output port in precisely the same order that they were written in at its input port; that is, according to a first-in, first out (fifo) queue dis cipline. since the addres sing sequence for a fifo devices memory is internally predefined, no external addressing information is required for the opera- tion of the lh540203 device. drop-in-replacement compatibility is maint ained with both larger sizes and smaller sizes of industry-standard nine-bit asynchronous fifos. the only change is in the number of internally-stored data words implied by the states of the full flag and the half-full flag. the retransmit ( rt) control signal causes the internal fifo-memory-array read-address pointer to be set back to zero, to point to the lh540203s first physical memory locati on, without affecting the i nternal fifo -memory- array write-address pointer. thus, the retransmit control signal provides a mechanism whereby a block of data, delimited by the zero physical addr ess and the current write-address-pointer value, may be read out repeatedly an arbitrary number of times. the only restrictions are that neither the read-address pointer nor the write-address pointer may wrap around during this entire process, i.e., advance past physical location zero after traversing the entire memory. the retransmit facility is not available when an lh540203 is operating in a depth-expanded configuration. the reset ( rs) control signal returns the lh540203 to an initial state, empty and re ady to be filled. an lh540203 should be reset during every system power-up sequence. a reset operation causes the internal fifo- memory-array write-address pointer, as well as the read- address pointer, to be set back to zero, to point to the lh540203s f irst ph ysical memory location. any informa- tion which previously had been stored within the lh540203 is not recoverable after a reset operation. a cascading (depth-expansion) scheme may be imple- mented by using the expansion in ( xi) input signal and the expansion out ( xo/ hf) output signal. this allows a deeper effective fifo to be implemented by using two or more lh540203 devices, without incurring additional latency (fallthrough or bubblethrou gh) delays, and with- out the necessity of storing and retrieving any given data word more than once. in this cascaded operating mode, one lh540203 device must be designated as the first- load or master device, by gr ounding its first-load ( fl/ rt) control input; the remaining lh540203 devices are designated as slaves, by tying their fl/ rt inputs high. because of the need to share control signals on pins, the half-full flag and the retransmission ca pability are not available for either master or slave lh54 0203 devices operating in cascaded mode. functional description (contd) data outputs q 0 - q 8 flag logic write pointer read pointer data inputs d 0 - d 8 dual-port ram array 2048 x 9 ef ff . . . 540203-1 input port control r w reset logic rs output port control expansion logic xo/hf xi fl/rt figure 3. lh540 203 block diagram lh540203 cmos 2048 9 asynchronous fifo 2
operational description reset the lh540 203 is reset when ever the reset input ( rs) is taken low. a reset operation init ializes both the read- address pointer and the write-address pointer to point to location zero, the first physical memory location. during a reset operation, the state of the xi and fl/ rt inputs determines whether the device is in standalone mode or in depth-cascaded mode. (see tables 1 and 2.) the reset operation forces the empty flag ef to be asserted ( ef = low), and the half- full flag hf and the full flag ff to be deasserted ( hf = ff = high); the data out pins (d 0 C d 8 ) are forced into a high-im peda nce state. a reset operation is required when ever the lh540203 first is powered up. the read ( r) and write ( w) inputs may be in any state when the reset operation is initiated; but they must be high, before the reset operation is terminated by a rising edge of rs, by a time t rrss (for read) or t wrss (for write) respectively. (see figure 10.) write a write cycle is initiated by a fal ling edge of the write ( w) control input. data setup times and hold times must be observed for the data inputs (d 0 C d 8 ). write opera- tions may occur independen tly of any ongoing read op- erations. however, a write operation is possible only if the fifo is not full, (i.e., if the full flag ff is high). at the falling edge of w for the first write operation after the memory is half filled, the half-full flag is asserted ( hf = low). it remains asserted until the difference between the write pointer and the read pointer indicates that the data words remaining in the lh54 0203 are fi lling the fifo memory to less than or equal to one-half of its total capacity. the half-full flag is deasserted ( hf = high) by the appropriate r ising edge of r. (see table 3.) the full flag is asserted ( ff = low) at the falling edge of w for the write operat ion which fills the last available location in the fifo memory array. ff = low inhibits further write operations until ff is cleared by a valid read operation. the full flag is deasserted ( ff = high) after the next rising edge of r releases another memory loca- tion. (see table 3.) read a read cycle is initiated by a falling e dge of the read ( r) control input. read data becomes valid at the data outputs (q 0 C q 8 ) after a time t a from the falling edge of r. after r goes high, the data outputs return to a high-impedance state. read operations may occur inde- pendently of any ongoing write operations. however, a read operation is possible only if the fifo is not empty (i.e., if the empty flag ef is high). the lh540203s internal read-address and write- address pointers operate in such a way that consecutive read operations always access data words in the same order that they were written. the empty flag is asserted ( ef = low) after that falling edge of r which accesses the last available data word in the fifo m emory. ef is deasserted ( ef = high) after the next rising edge of w loads another valid data word. (see table 3.) data flow-through read-data flow-through mode occurs when the read ( r) control input is bro ught low while the fifo is empty, and is held low in anticipation of a write cycle. at the end of the next write cycle, the empty flag ef momentarily is deasserted, and the data word just written becomes available at the data outputs (q 0 C q 8 ) after a maxi- mum time of t wef + t a . additional write operations may occur while the r input remains low; but only data from the first write operation flows through to the data outputs. additional data words, if any, may be accessed only by toggling r. write-data flow-through mode occurs when the write ( w) input is brought low while the fifo is full, and is held low in anticipation of a read cycle. at the end of the read cycle, the full flag momentarily is deasserted, but then immediately is reasserted in response to w being held low. a data word is written into the fifo on the rising edge of w, which may occur no sooner than t rff + t wpw after the read operation. pin descriptions pin pin type 1 description d 0 C d 8 i input data bus q 0 C q 8 o/z output data bus w i write request r i read req uest ef o empty flag ff o full flag pin pin type 1 description xo/ hf o expansion out/half-full flag xi i expansion in fl/ rt i first load /retransmit rs i reset v cc v positive power supply v ss v ground note: 1. i = input, o = output, z = high-imp edance, v = power voltage level cmos 2048 9 asynchronous fifo lh540203 3
operational description (contd) retransmit the fifo can be made to reread previously-read data by means of the retransmit function. a retransmit opera- tion is initiated by pulsing the rt input low. both r and w must be deasserted (high) for the duration of the retransmit pulse. the fifos internal read-address pointer is reset to point to location zero, the first physical memory location, while the internal write- address pointer remains unchanged. after a retransmit operation, those data words in the region in between the read-address pointer and the write-address pointer may be reaccessed by subsequent read operations. a retransmit operation may affect the state of the status flags ff, hf, and ef, depending on the relocation of the read-address pointer. there is no restriction on the number of times that a block of data within an lh540203 may be read out, by repeating the retransmit operation and the subsequent read operations. the maximum length of a data block which may be retransmitted is 2048 words. note that if the write-address pointer ever wraps around (i.e., passes location zero more than once) during a sequence of retransmit opera- tions, some data words will be lost. the retransmit function is not available when the lh540203 is operating in depth-cascaded mode, because the fl/ rt control pin must be used for first-load selection rather than for retransmission control. table 1. grouping-mode determination during a reset operation xi fl/ rt mode xo/ hf usage xi usage fl/ rt usage h 1 h cascaded slave 2 xo xi fl h 1 l cascaded master 2 xo xi fl l x standalone hf (none) rt notes: 1. a reset operation forces xo high for the n th fifo, thus forcing xi high for the (n+1) st fifo. 2. the terms master and slave refer to operation in depth-cas- caded grouping mode. 3. h = high; l = low; x = dont care. table 2. expansion-pin usage according to grouping mode i/o pin standalone cascaded master cascaded slave i xi grounded from xo (n-1st fifo) from xo (n-1st fifo) o xo/ hf becomes hf to xi (n+1st fifo) to xi (n+1st fifo) i fl/ rt becomes rt grounded (logic low) logic high table 3. status flags number of unread data words present within 2048 9 fifo ff hf ef 0hhl 1 to 1024 h h h 1025 to 2047 h l h 2048 l l h lh540203 cmos 2048 9 asynchronous fifo 4
operational modes standalone configuration when depth cascading is not required for a given application, the lh540203 is pla ced in st andalone mode by tying the expansion in input ( xi) to ground. this input is internally sampled during a reset operation. (see table 1.) width expansion word-width expansion is implemented by placing mul- tiple lh540203 devices in parallel. each lh540203 should be configured for standalone mode. in this ar- rangement, the behavior of the status flags is identical for all devices; so, in principle, a representative value for each of these flags could be derived from any one device. in practice, it is better to derive composite flag values using external logic, since there may be minor speed variations between different actual devices. (see figures 4, 5, and 6.) write data in d 0 - d 8 9 full flag reset xi rt retransmit empty flag 9 read hf lh540203 w ff rs r ef data out q 0 - q 8 540203-17 figure 4. standalone fifo (2048 9) 18 write full flag reset 9 read empty flag r ef xi rt r w 540203-18 rs retransmit rt xi hf w ff rs 9 18 9 hf 9 lh540203 lh540203 data in d 0 - d 17 data out q 0 - q 17 figure 5. fifo word-width expans ion (2048 18) cmos 2048 9 asynchronous fifo lh540203 5
operational modes (contd) depth cascading depth cascading is implemented by configuring the required number of lh540 203s in depth-cascaded mode. in this arrangement, the fifos are connected in a circular fashion, with the expansion out output ( xo) of each device tied to the expansion in input ( xi) of the next device. one fifo in the cascade must be designated as the first-l oad dev ice, by tying its first load input ( fl/ rt) to ground. all other devices must have their fl/ rt inputs tied high. in this mode, w and r signals are shared by all devices, while logic within each lh540203 controls the steering of data. only one lh540203 is enabled during any given write cycle; thus, the common data in inputs of all devices are tied together. likewise, only one lh540203 is enabled during any given read cycle; thus, the common data out outputs of all devices are wire- ored together. in depth-cascaded mode, external logic should be used to generate a compo site full flag and a composite empty flag, by anding the ff outputs of all lh540203 devices together and anding the ef outputs of all devices together. since ff and ef are assertive-low signals, this anding actually is implemented using an asser- tive-high physical or gate. the half-full flag and the retransmit function are not available in depth-cascaded mode. lh540203 rs rs ff 9 9 rs w ff rs ff 9 9 9 r 9 fl fl ef xi xo fl ef vcc vcc xo xo 9 9 xi 540203-19 xi empty full ef lh540203 lh540203 data in d 0 - d 8 data out q 0 - q 8 figure 6. fifo depth cascading (6144 9) lh540203 cmos 2048 9 asynchronous fifo 6
operational modes (contd) compound fifo expansion a combination of word-width expansion and depth cascading may be implemented easily by operating groups of depth-cascaded fifos in parallel. bidirectional fifo operation bidirectional data buffering between two systems may be implemented by operating lh540203 devices in par- allel, but in opposite directions. the data in inputs of each lh540203 are tied to the corresponding data out outputs of another lh540203, which is operating in the opposite direction, to form a single bidirectional bus interface. care must be taken to assure that the appropriate read, write, and flag signals are routed to each system. both word- width expansion and depth cascading may be used in bidirectional applications. lh540203 depth expansion block lh540203 depth expansion block lh540203 depth expansion block q 0 - q 8 data out d n-9 - d n-1 d 18 - d n-1 d 9 - d n-1 d 0 - d n-1 data in r w rs q 0 - q n-1 q 0 - q 17 540203-20 array stores n-bit words. q 0 - q n-10 figure 7. com pound fifo expansion lh540203 lh540203 system a system b qb 0 - 8 db 0 - 8 da 0 - 8 qa 0 - 8 xi wb ra efa hfa rta rs ffb rtb hfb efb rb 540203-21 xi wa ffa rs figure 8. bidirectional fifo operation (2048 9 2) cmos 2048 9 asynchronous fifo lh540203 7
absolute maximum ratings 1 parameter rating supply voltage to v ss potential C0.5 v to 7 v signal pin voltage to v ss potential 2 C0.5 v to v cc + 0.5 v (not to exceed 7 v) dc output current 3 50 ma storage temperature range C65 o c to 150 o c power dissipation (package limit) 1.0 w dc voltage applied to outputs in high-z state C0.5 v to v cc + 0.5 v (not to exceed 7 v) notes: 1. stresses greater than those listed under a bsol ute maximum ratings may cause perman ent damage to the device. this is a stress rating for transient c ondi tions only. functi onal operation of the device at these or any other conditions outside of those indicated in the operating ra nge of this specifi cation is not implied. expo sure to a bsol ute ma ximum rating conditions for extended p eriods may affect reliability. 2. negative undershoots of 1.5 v in amplitude are permitted for up to 10 ns once per cycle. 3. outputs should not be shorted for more than 30 seconds. no more than one output should be shorted at any time. operating range symbol parameter min max unit t a temperature, ambient 070 c v cc supply voltage 4.5 5.5 v v ss supply voltage 00v v il logic low input voltage 1 C0.5 0.8 v v ih logic high input voltage 2.0 v cc + 0.5 v note: 1. negative undershoots of 1.5 v in amplitude are permitted for up to 10 ns once per cycle. dc electrical characteristics (over operat ing range) symbol parameter test conditions min max unit i li input leakage current v cc = 5.5 v, v in = 0 v to v cc C10 10 m a i lo output leakage current r 3 v ih , 0 v v out v cc C10 10 m a v oh output high voltage i oh = C2 .0 ma 2.4 v v ol output low voltage i ol = 8.0 ma 0.4 v i cc average supply current 1 measured at f = 40 mhz 100 ma i cc2 average standby current 1 all inputs = v ih 15 ma i cc3 power down current 1 all inputs = v cc C 0.2 v 5ma note: 1. i cc , i cc 2 , and i cc3 are dep endent upon actual o utput loading and cycle rates. s pecified values are with outputs open. lh540203 cmos 2048 9 asynchronous fifo 8
ac test conditions parameter ra ting input pulse levels v ss to 3 v input rise and fall times ( 10% to 90%) 5 ns input t iming reference levels 1.5 v output reference levels 1.5 v output load, timing tests figure 9 capacitance 1,2 parameter ra ting c in (input capacitance) 5 pf c out (output capacitance) 7 pf notes: 1. sample tested only. 2. capacitances are maximum values at 25 o c, measured at 1.0 mhz, with v in = 0 v. 540203-4 device under test +5 v 30 pf 1.1 k w 680 w includes jig and scope capacitances * * figure 9. output load circuit cmos 2048 9 asynchronous fifo lh540203 9
ac electrical characteristics 1 (over operating range) symbol parameter t a = 15 ns t a = 20 ns t a = 25 ns t a = 35 ns t a = 50 ns unit min max min max min max min max min max read cycle timing t rc read cycle time 25C30C35C45C65Cns t a access time C15C20C25C35C50ns t rr read recovery time 10C10C10C10C15Cns t rpw read pulse width 2 15C20C25C35C50Cns t rlz data bus active from read low 3 5C5C5C5C5Cns t wlz data bus active from write high 3,4 10C10C10C10C10Cns t dv data valid from read pulse high 5C5C5C5C5Cns t rhz data bus high-z from read high 3 C15C15C15C15C20ns write cycle timing t wc write cycle time 25 C 30 C 35 C 45 C 65 C ns t wpw write pulse width 2 15C20C25C35C50Cns t wr write recovery time 10C10C10C10C15Cns t ds data setup time 12C12C12C15C20Cns t dh data hold time 0C0C0C0C0Cns reset timing t rsc reset cycle time 25C30C35C45C65Cns t rs reset pulse width 2 15C20C25C35C50Cns t rsr reset recovery time 10C10C10C10C15Cns t rrss read high to rs high 15C20C25C35C50Cns t wrss write high to rs high 15C20C25C35C50Cns retransmit timing 5 t rtc retransmit cycle time 25 C 30 C 35 C 45 C 65 C ns t rt retransmit pulse width 2 15C20C25C35C50Cns t rtr retransmit recovery time 10 C 10 C 10 C 10 C 15 C ns flag timing t efl reset low to empty flag low C 25 C 30 C 35 C 45 C 65 ns t hfh,ffh reset low to half-full and full flags high C25C30C35C45C65ns t ref read low to empty flag low C15C20C25C35C45ns t rff read high to full flag high C 15 C 20 C 25 C 35 C 45 ns t wef write high to empty flag high C 15 C 20 C 25 C 35 C 45 ns t wff write low to full flag low C 15 C 20 C 25 C 35 C 45 ns t whf write low to half-full flag low C15C20C25C35C45ns t rhf read high to half-full flag high C15C20C25C35C45ns expansion timing t xol expansion out low C 18 C 20 C 25 C 35 C 50 ns t xoh expansion out high C18C20C25C35C50ns t xi expansion in pulse width 15C20C25C35C50Cns t xir expansion in recovery time 10C10C10C10C10Cns t xis expansion in setup time 7 C 10 C 10 C 15 C 15 C ns notes: 1. all timing measurements are performed at ac test condition levels. 2. pulse widths less than minimum value are not allowed. lh540203 cmos 2048 9 asynchronous fifo 10
timing diagrams t rs efl t rsr t rrss t wrss t ffh t hfh t , rs r,w ef ff,hf 540203-14 t rsc notes: 1. t rsc = t rs + t rsr . 2. w and r 3 v ih around the rising edge of rs. 3. the data out pins (d 0 - d 8 ) are forced into a high-impedance state whenever ef = low. figure 10. reset timing w t wpw t rlz t a t wc t a t rpw t dv t rhz valid data out t rr r t rc t wr t dh t ds valid data in 540203-5 q 0 - q 8 d 0 - d 8 valid data out valid data in figure 11. a synchronous write and read operation cmos 2048 9 asynchronous fifo lh540203 11
timing diagrams (contd) ff r w t rff t wff last write first read 540204-6 figure 12. full flag from last write to first read ef w r t wef t ref last read first write 540203-7 note: the data out pins (d 0 - d 8 ) are forced into a high-impedance state whenever ef = low. figure 13. empty flag from last read to first write lh540203 cmos 2048 9 asynchronous fifo 12
timing diagrams (contd) valid data in rpe t wef t ref t wlz t a t 540203-8 w r ef d 0 - d 8 q 0 - q 8 valid data out notes: 1. t rpe = t rpw 2. t rpe : effective read pulse width after empty flag high. 3. the data out pins (d 0 - d 8 ) are forced into a high-impedance state whenever ef = low. figure 14. read data flow-through wpf t 540203-9 r w ff t wff t rff t dh t ds t a d 0 - d 8 q 0 - q 8 notes: 1. t wpf = t wpw. 2. t wpf : effective write pulse width after full flag high. valid data in valid data out figure 15. write data flow-through cmos 2048 9 asynchronous fifo lh540203 13
timing diagrams (contd) t wef w t rpe ef r 540203-10 notes: 1. t rpe = t rpw 2. t rpe : effective read pulse width after empty flag high. 3. the data out pins (d 0 - d 8 ) are forced into a high-impedance state whenever ef = low. figure 16. empty flag timing r ff w 540203-11 notes: 1. t wpf = t wpw. 2. t wpf : effective write pulse width after full flag high. t rff t wpf figure 17. full flag timing hf w r t rhf t whf 540203-12 half-full or less more than half-full half-full or less figure 18. half-full flag timing lh540203 cmos 2048 9 asynchronous fifo 14
timing diagrams (contd) rt t rtr t rt r,w 540203-13 notes: 1. t rtc = t rt + t rtr . 2. ff, hf, and ef may change state during retransmit; but they will become valid by t rtc . figure 19. retransmit timing t xol t xoh read from last valid location t xoh t xol xo 540203-15 write to last available location w r figure 20. expansion-out timing t xis r 540203-16 xi w write to first available location t xis read from first valid location t xir t xi figure 21. expansion-in timing cmos 2048 9 asynchronous fifo lh540203 15
package diagrams 28dip-3 7.49 [0.295] 7.11 [0.280] 0.51 [0.020] min 4.57 [0.180] max 3.43 [0.135] 3.18 [0.125] 2.54 [0.100] typ. 0.53 [0.021] 0.38 [0.015] 0.30 [0.012] 0.20 [0.008] detail dimensions in mm [inches] 34.80 [1.370] 34.54 [1.360] 0 to 15 maximum limit minimum limit 3.30 [0.130] 7.62 [0.300] typ. 28dip (dip28-w-300) 28-pin, 300-mil pdip 28soj300 dimensions in mm [inches] maximum limit minimum limit 28soj (soj28-p-300) 1.27 [0.050] typ. 0.53 [0.021] 0.33 [0.013] detail 7.9 [0.311] 7.5 [0.295] 8.63 [0.340] 8.23 [0.324] 18.7 [0.736] 18.3 [0.720] 1.15 [0.045] 0.85 [0.033] 0.64 [0.025] min 7.0 [0.276] 6.6 [0.260] 2.6 [0.102] 2.2 [0.087] 3.7 [0.146] 3.3 [0.130] 0.20 [0.008] 0.8 [0.031] 0.6 [0.024] 0.102 [0.004] 114 28 15 28-pin, 300-mil soj lh540203 cmos 2048 9 asynchronous fifo 16
ordering information 15 20 25 35 50 lh540203 device type x package - ## speed 540203md cmos 2048 x 9 fifo example: lh540203u-25 (cmos 2048 x 9 fifo, 32-pin plcc, 25 ns) access time (ns) d 28-pin, 300-mil plastic dip (dip28-w-300) k 28-pin, 300-mil soj * (soj28-p-300) u 32-pin plastic leaded chip carrier (plcc32-p-r450) * contact a sharp representative for availability of soj package. 1.27 [0.050] 4 sides bsc 14.05 [0.553] 13.89 [0.547] 15.11 [0.595] 14.86 [0.585] 11.51 [0.453] 11.35 [0.447] 12.57 [0.495] 12.32 [0.485] 3.56 [0.140] 3.12 [0.123] 2.41 [0.095] 1.52 [0.060] 0.81 [0.032] 0.66 [0.026] 0.53 [0.021] 0.33 [0.013] 32plcc maximum limit minimum limit dimensions in mm (inches) 0.38 [0.015] min detail 10.92 [0.430] 9.91 [0.390] 13.46 [0.530] 12.45 [0.490] 0.10 [0.004] 32plcc (plcc32-p-r450) 32-pin, 450-mil plcc cmos 2048 9 asynchronous fifo lh540203 17

▲Up To Search▲

Price & Availability of LH540203D20

	To Download LH540203D20 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .